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| 100350 Low Power Hex D-Type Latch July 1988 Revised August 2000 100350 Low Power Hex D-Type Latch General Description The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid data present on its D input before Ea or Eb went HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 k pull-down resistors. Features s 20% power reduction of the 100150 s 2000V ESD protection s Pin/function compatible with 100150 s Voltage compensated operating range = -4.2V to -5.7V Ordering Code: Order Number 100350PC 100350QC Package Number N24E V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devises also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions 28-Pin PLCC Pin Names D0-D5 Ea , Eb MR Q0-Q5 Q0-Q5 Data Inputs Common Enable Inputs (Active LOW) Asynchronous Master Reset Input Data Outputs Complementary Data Outputs Description (c) 2000 Fairchild Semiconductor Corporation DS009884 www.fairchildsemi.com 100350 Truth Tables (Each Latch) Latch Operation Inputs Dn L H X X Ea L L H X Eb L L X H MR L L L L Outputs Qn L H Latched (Note 1) Latched (Note 1) Dn X Asynchronous Operation Inputs Ea X Eb X MR H Outputs Qn L H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Note 1: Retains data present before E positive transition Logic Diagram www.fairchildsemi.com 2 100350 Absolute Maximum Ratings(Note 2) Above which the useful life may be impaired. Storage Temperature (TSTG) -65C to +150C Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) Recommended Operating Conditions Case Temperature (TC) Supply Voltage (VEE) 0C to +85C +150C -7.0V to +0.5V VEE to +0.5V -5.7V to -4.2V -50 mA 2000V Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. DC Electrical Characteristics Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current MR Dn Ea, Eb IEE Power Supply Current (Note 4) Min Typ -955 -1705 Max -870 -1620 -1610 Units mV mV mV mV A 240 240 240 Inputs Open -89 -93 -44 -44 mA VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V A VIN = VIH (Max) VIN =VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) Conditions Loading with 50 to -2.0V Loading with 50 to -2.0V VEE = -4.5V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C -1025 -1830 -1035 -1165 -1830 0.50 -870 -1475 Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) Note 4: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions. DIP AC Electrical Characteristics VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dn to Output (Transparent Mode) Propagation Delay Ea, Eb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time D0-D5 MR (Release Time) tH tPW(L) tPW(H) Hold Time, D0-D5 Pulse Width LOW Ea, Eb Pulse Width HIGH, MR 1.00 1.60 0.40 2.00 2.00 1.00 1.60 0.40 2.00 2.00 1.00 1.60 0.40 2.00 2.00 ns ns ns Figure 4 Figure 2 Figure 3 ns Figures 3, 4 0.75 0.90 0.35 1.85 2.10 1.30 0.75 0.90 0.35 1.85 2.10 1.30 0.75 0.90 0.35 2.05 2.10 1.30 ns ns ns Figures 1, 3 Figures 1, 2 0.50 1.40 0.50 1.40 0.50 1.50 ns Figures 1, 2 TC = 0C Min Max TC = +25C Min Max TC = +85C Min Max Units Conditions 3 www.fairchildsemi.com 100350 PLCC AC Electrical Characteristics VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dn to Output (Transparent Mode) Propagation Delay Ea, Eb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time D0-D5 MR (Release Time) tH tPW(L) tPW(H) Hold Time, D0-D5 Pulse Width LOW Ea, Eb Pulse Width HIGH, MR 0.90 1.50 0.30 2.00 2.00 0.90 1.50 0.30 2.00 2.00 0.90 1.50 0.30 2.00 2.00 ns ns ns Figure 4 Figure 2 Figure 3 ns Figures 3, 4 0.75 0.90 0.35 1.65 1.90 1.10 0.75 0.90 0.35 1.65 1.90 1.10 0.75 0.90 0.35 1.85 1.90 1.10 ns ns ns Figures 1, 3 Figures 1, 2 0.50 1.20 0.50 1.20 0.50 1.30 ns Figures 1, 2 TC = 0C Min Max TC = +25C Min Max TC = +85C Min Max Units Conditions Test Circuit Note: * * * * * * VCC, VCCA = +2V, VEE = -2.5V L1 and L2 = equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 F from GND to VCC and VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF FIGURE 1. AC Test Circuit www.fairchildsemi.com 4 100350 Switching Waveforms FIGURE 2. Enable Timing FIGURE 3. Reset Timing Notes: tS is the minimum time before the transition of the enable that information must be present at the data input. tH is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Time 5 www.fairchildsemi.com 100350 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 6 100350 Low Power Hex D-Type Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
Price & Availability of 100350
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